The invention relates to a data conversion system, and more particularly to a sigma-delta modulator, data conversion system and method with dynamic element matching logic.
Data conversion techniques have been in existence for many years, and their use has become widespread. Converters used, such as a digital-to-analog (D/A) converter or an analog-to-digital (A/D) converter, have found homes in applications such as communication systems, consumer and professional audio, and precision measurement devices.
Sigma-delta modulator (SDM), an A/D converter also known as an oversampling A/D converters characterized by high dynamic range and high resolution, has been successfully applied in communication and other signal processing areas. One-bit sigma-delta modulators have been popular in the past for their inherent linearity. However, to fulfill the demand for higher resolution and wider bandwidth without increasing the oversampling ratio, it is necessary to utilize multi-bit sigma-delta modulators which also reduce quantization noise power. Nevertheless, the major drawback of the multi-bit sigma-delta modulators is non-linearity stemming from the mismatching between the D/A elements in the feedback multi-bit D/A converter of the SDMs. The mismatching between the D/A elements in the multi-bit D/A converter, such as capacitors, resistors, current sources and the like, due to manufacturing variations, imperfections in materials used, changes in temperature, humidity, degradation and so on, causes non-linearity in the feedback path, which manifests itself as distortion and noise at output.
One approach addressing non-linearity in multi-bit D/A converters is dynamic element matching (DEM). Dynamic element matching (DEM) randomly selects D/A elements in the multi-bit D/A converter to distribute the non-linear error across the spectrum. Moreover, a particular DEM technique is the data weighted average (DWA). The conventional DWA logic regularly selects the D/A elements of multi-bit converter one by one at a predetermined turn according to a digital input code of the converter. DWA technique averages the participation of each D/A element, thus shifting DAC (D/A converter) mismatch errors to a higher frequency band and providing easy implementation and first order noise shaping.
However, since the DWA logic depends on the amplitude of the input digital code, in-band tones occur when the input amplitude is small, reducing both the SNDR (signal-to-noise plus distortion ratio) and SFDR (spur free dynamic range) significantly. FIG. 1 shows a N-bit sigma-delta modulator 10, wherein N is an integer greater than 2, effectively removing in-band tones, and thus increasing the in-band efficiency of sigma-delta modulators. The N-bit sigma-delta modulator 10 is disclosed in commonly assigned U.S. patent application Ser. No. 11/152,132 filed Jun. 14, 2005, entitled “Sigma-delta modulator, D/A conversion system and dynamic element matching method”, incorporated herein by reference. The sigma-delta modulator 10 comprises a summing junction 12, a loop filter 14, an N-bit quantizer 16, an N-bit D/A converter 18 and a dynamic element matching logic 22. The summing junction 12 receives an analog input signal Vin and subtracts an analog feedback signal VFB from the N-bit D/A converter 18. The loop filter 14 coupled to the summing junction 12, receiving the output of the summing junction 12, includes cascaded analog integrator stages and generates a filtered analog output to the N-bit quantizer 16. The N-bit quantizer 16 then quantizes the analog output of the loop filter 14 and generates a digital code, also fed back to the N-bit D/A converter 18. The N-bit D/A converter 18, having a plurality of D/A elements, convertes the digital code to the analog feedback signal VFB to the summing junction 12. The dynamic element matching logic 22 coupled between the N-bit quantizer 16 and N-bit D/A converter 18. The operation of the dynamic element matching logic 22 is described in the following.
It is assumed that the N-bit D/A converter 18 includes 8 D/A elements, C1˜C8. The dynamic element matching logic 22 divides the D/A elements into groups, wherein the number of the groups is prime to the number of the D/A elements. For example, if there are 8 D/A elements in the D/A converter 18, the dynamic element matching logic 22 divides C1˜C8 into 3, 5, or 7 groups. FIG. 2 shows an exemplary dynamic element matching logic 22 with the D/A converter 18 including 8 D/A elements, wherein the dynamic element matching logic 22 divides the D/A elements into 3 groups. In FIG. 2, the y-axis denotes the digital code input at every time slot and the grey blocks on the x-axis and the numerals therein denote corresponding selected elements and selected orders. The dynamic element matching logic 2.2 divides C1˜C8 into 3 groups wherein C1˜C3 is the first group, C4˜C5 is the second, and C6˜C8 is the third. When receiving digital code from the N-bit quantizer 16, the dynamic element matching logic 22 selects groups and the D/A elements therein according to the digital code, and the previous selection of group and D/A element, and the number of selected dynamic elements corresponds to the digital code. For example, when the input code is 5 at time t1, the dynamic element matching logic 22 selects C1 from the first group, C4 from the second group, C6 from the third group, C2 from the first group, and C5 from the second group accordingly in the turn of the arrow. When the input code is 2 at time t2, starting from the D/A element succeeding the previous last selected D/A element of the group succeeding the previous last selected group (i.e. C7 in the third group), the dynamic element matching logic 22 proceeds to select C7 from the third group and C3 from the first group accordingly.
Although the described dynamic element matching logic removes in-band tones, it may, however, select the same D/A element repeatedly with large input signal amplitude. FIG. 3 shows another example of the dynamic element matching logic 22 of FIG. 2. As shown in FIG. 3, the dynamic element matching logic 32 also divides C1˜C8 into 3 groups wherein C1˜C3 is the first group, C4˜C5 is the second, and C6˜C8 is the third. When the input code is 4 at time t2, the dynamic element matching logic 32 selects C2, C5, C7 and C3 in turn. When the input code is 7 at time t3, the dynamic element matching logic 22 proceeds to select C4, C8, C1, C5, C6, C2 and C5 in turn. It is observed that the dynamic element matching logic 22 selects the D/A element C5 twice. Typically, the frequency of the operating clock is increased to solve this problem, this, however, complicates the circuits and increases the costs. Consequently, a simple method for solving described problem without extra effort that maintains the performance of the described dynamic element matching logic is desired.